The present invention relates to a data processor system for processing data presented in digital form, provided with at least one data processor unit which comprises at least one processor module having processor elements which operate in parallel in time, including at least one arithmetic and/or logic processor element and at least one memory processor element, and a reconfigurable switching matrix (crossbar switch) to which input signals for the processor module and output signals from the processor elements belonging to the respective processor module can be fed and from which input signals for the processor elements belonging to said processor module and output signals of said processor module can be obtained, the arithmetic and/or logic processor element being provided, moreover, with an ALU (arithmetic and/or logic element) and a program memory, and the ALU having a first and a second input (P and Q respectively) via which data can be fed, and a third input (I) via which instructions can be fed in for the operations to be executed in the ALU relating to the data fed in.
The article entitled "Warp Architecture and Implementation" by M. Annaratone et al from the "13th Annual symposium on computer architecture, June 1986, Tokyo (Japan)" discloses a "systolic array computer (Warp)" in which a row of processor units is present and each processor unit is provided with at least one arithmetic and logic processor element and at least one memory processor element, a crossbar switch futhermore being present to which, via a buffer circuit, input signals for a processor unit and output signals from the processor elements belonging to the respective processor unit can be fed and from which input signals for processor elements belonging to said processor unit and output signals from said processor unit can be obtained. The arithmetic and logic processor element is provided in the usual manner with an ALU in order to be able to execute diverse arithmetic and logic operations, a separate arithmetic processor element (multiplier) being present to execute multiplications.
From the point of view of simplicity, it is desirable to define beforehand in the programs in the respective program memories at which instant which operations take place in the processor elements; more particularly, this is desirable if the data processor system is used in installations operating on a real-time basis, such as, for example, video processor systems. A condition for this is, however, that the programs are formed by fixed cycles of branch-free instructions as a result of which the latter do not make any conditional operations possible. This is found to be a serious drawback which appreciably limits the possible applications of the data processor system.